The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 1994
Filed:
May. 15, 1992
Johannes A De Poorter, Eindhoven, NL;
Adriaan Valster, Eindhoven, NL;
U.S. Philips Corp., New York, NY (US);
Abstract
A semiconductor device includes a semiconductor structure (D3) of parallel semiconductor layers on a semiconductor substrate (1), in which layers a mesa (12) is formed which includes only a portion (D1) of the semiconductor layer structure (D3). Such devices as are useful in optoelectronic devices in which the mesa (12) forms part of a semiconductor diode laser or a radiation waveguide. During cleaving of such devices, for example for the formation of a mirror surface, damage often arises near the mesa (12), which is undesirable. The mesa (12), which projects from the device, is also easily damaged during further manipulation of the device. The semiconductor layer structure (D3) includes a sunken region (11) within which the semiconductor layer structure (D3) is at least partly recessed in the substrate (1), while the mesa (12) is positioned within the boundaries of the sunken region (11). As a result, the mesa (12) is also recessed at least partly, and thus is at least partly protected. In addition, less damage occurs near the mesa (12) during cleaving. When the mesa (12) is entirely recessed, the device is in addition particularly suitable for upside-down final mounting. In a method of making the device, a recess (11) is provided in the substrate (1) before the semiconductor layer structure (D3) and the mesa (12) therein are provided. This method is very simple and gives a high yield of devices having the required characteristics.