The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 1994

Filed:

Jun. 19, 1991
Applicant:
Inventor:

Takeshi Shima, Sagamihara, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
365 45 ; 365185 ;
Abstract

An analog storage device employs an electrically erasable programmable transistor as its memory cell. The memory cell transistor has a source and a drain which are disposed spaced apart from each other on a semiconductive substrate to define a channel region therebetween, an insulated floating gate electrode which at least overlaps the channel region, and an insulated control gate electrode disposed above the insulated floating gate electrode. Minority carriers are allowed to tunnel between the channel region and the insulated floating gate. The amount of carriers to be stored on the floating gate electrode is controlled such that it is in proportion to analog data to be stored therein. A variation in the internal field of the transistor which may occur when its floating gate electrode is being charged with minority carriers is monitored. When a field variation is detected, a voltage for compensating for the detected field variation is applied to the control gate electrode, whereby the linearity of analog storage is ensured.


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