The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 1994
Filed:
Dec. 30, 1992
David R Van Loan, Diamond Bar, CA (US);
Charles J Johnston, Walnut, CA (US);
Mark A Swart, Upland, CA (US);
Everett Charles Technologies, Inc., Pomona, CA (US);
Abstract
Integrated circuit (IC) packages mounted on a loaded printed circuit board (PCB) are tested by a translator module by first placing a corresponding module over each package. Each module has rows of spring contacts for releasably contacting corresponding electrical leads adjacent opposite sides of the IC package. An upper surface of the module has an array of electrically conductive test pads internally connected to corresponding contacts on the module. The test pads match an array of spring probes in the test unit. The module can be a molded plastic housing with metal leaf spring contacts, or it can comprise a composite flex-circuit material with individual contacts comprising flexible spring-like metalized plastic fingers. Contacts on the test module can releasably engage the leads on the IC package directly, or they can contact separate conductive leads on the PCB adjacent the leads on the IC package. During testing, the spring probes contact the test pads on the test modules and circuit continuity is established via the electrical connections from the spring probes through the modules to the leads adjacent the IC packages. The modules translate dense in-line spacing of leads adjacent the IC packages to the oversized in-line spacing of test pads on the module. In another embodiment, the translator module is attached to a flex-circuit cable coupled to the test system electronics. The translator module is manually placed over each IC package during testing. In a further embodiment, an integrated circuit package contains a built-in test verifier system so that standard test probes can be used to test the package without use of a separate translator module.