The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 1994
Filed:
Feb. 04, 1992
Deepraj S Puar, Sunnyvale, CA (US);
Cirrus Logic, Inc., Fremont, CA (US);
Abstract
A circuit is added to a complementary metal-oxide silicon (CMOS) integrated circuit (IC) to provide an intentional, non-reverse-biased VDD-to-VSS shunt path for transient currents such as electrostatic discharges (ESD). This circuit protects the IC from ESD damage by turning on before any other path, thus directing the ESD transient current away from easily damaged structures. Specifically, the ESD transient current is steered from the VDD rail to the VSS rail through the on conduction of a P-channel transistor whose source and drain are connected to VDD and VSS respectively. The voltage on the gate of this transistor follows the VDD supply rail because it is driven by a delay network formed by a second transistor and a capacitor. This VDD-tracking delay network turns the VDD-to-VSS transistor on during a transient and off during normal operation of the IC.