The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 1994

Filed:

Mar. 26, 1991
Applicant:
Inventors:

Yasushi Takahashi, Tachikawa, JP;

Kazuyuki Miyazawa, Iruma, JP;

Hidetoshi Iwai, Ohme, JP;

Masaya Muranaka, Akishima, JP;

Yoshitaka Kinoshita, Kokubunji, JP;

Satoru Koshiba, Tokyo, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H02G / ;
U.S. Cl.
CPC ...
257676 ; 257692 ; 257696 ; 257773 ; 257787 ; 174 524 ; 361813 ; 365 51 ;
Abstract

According to one aspect of the present invention, a semiconductor chip, which can be mounted in a zigzag in-line type package (ZIP) partially using a tabless lead frame, includes bonding pads arranged on the chip so that the chip can be applied also to other different types of packages. These different types of packages include a small out-line J-bent type package (SOJ) which uses a lead frame with tab, and a dual in-line type package (DIP) which uses a tabless lead frame. Further, a plurality of bonding pad pairs are provided amongst the bonding pads on the chip, each pad of such bonding pad pairs having the same function as the other pad associated therewith thereby duplicating a common function in different bonding pads on the semiconductor chip so as to make the semiconductor chip compatible with a variety of or different types of packages. In accordance with another aspect of the invention, a resin-encapsulated semiconductor device of the ZIP structure is provided in which a semiconductor pellet having a plurality of external terminals disposed on a device-forming surface along each side of the planar shape is encapsulated with a resin, wherein inner leads for signals connected electrically with external terminals, disposed opposing to the surface of the resin-encapsulated portion disposed with outer leads and disposed along the most remote side of the semiconductor pellet, are arranged so as to overlap the semiconductor pellet.


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