Method for etching improved contact openings to peripheral circuit

Abstract

A method is described for etching contact openings through first and second interlevel dielectric layers covering the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. There is provided within and over the semiconductor wafer DRAM integrated circuit including peripheral circuits to be electrically contacted. A first conductive layer is formed over the DRAM integrated circuit and the layer is patterned. A first interlevel dielectric layer is formed over the first conductive layer which has been patterned. The first interlevel layer is composed of in the order from the first conductive layer of a silicon oxide layer and a borophosphosilicate layer. A second conductive layer is formed over the first interlevel dielectric layer and the second conductive layer is patterning said second conductive layer. A second interlevel dielectric layer is formed over the exposed second conductive layer and first interlevel dielectric. The second interlevel layer is composed of in the order from the second conductive layer of a borophosphosilicate layer and a silicon oxide layer. The openings through the first and second interlevel dielectric layers are etched to electrically contact regions in the peripheral circuits. The result due to the order of the interlevel dielectric layers the openings have an improved and positive slope characteristic.