The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 1994

Filed:

Jun. 11, 1993
Applicant:
Inventors:

Po Tong, Fremont, CA (US);

Peter A Ruetz, Redwood City, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 375 ;
Abstract

Sequential encoding of Reed-Solomon codes using a discrete time delay line, a single adder, and a single multiplier provides efficient encoding of Reed-Solomon codes with or without interleaving. The encoder utilizes a clock whose rate is r times the symbol rate where r is the redundancy of the code. The finite field operations are performed in a sequential manner requiring only one finite field multiplier and one finite field adder. All memory elements are consolidated into a discrete time delay line which can be implemented with a random access memory. The encoder can be easily reconfigured for changes in generator polynomial of the code, the amount of redundancy, and interleaving depth.


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