The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 1994
Filed:
Aug. 27, 1990
John S Hsu, Round Rock, TX (US);
Amr M Amin, Austin, TX (US);
Board of Regents, The University of Texas System, Austin, TX (US);
Abstract
Improved techniques and circuit arrangements are provided for generating gating signals for firing the switching devices of an inverter circuit or like power electronics generator to generate harmonics of a fundamental frequency source and for providing an adjustable phase offset between the harmonic and the fundamental signals. According to a line-frequency signal modification method, a set of line-frequency sine wave signals disposed at equidistant phase angles are generated from a multi-phase fundamental input voltage. Firing pulses are produced from the line-frequency signals by accurately detecting the points of zero-crossings for the signals and subsequently detecting the overlapping segments of similar polarity between successive line-frequency signals. Two different schemes for conveniently generating the required line-frequency sine wave signals are present. According to a digital technique, a series of logic counters are used to generate the required M-phase, Nth-order harmonic gate timing signals. A first counter is used to generate a train of a predefined number of equidistant pulses corresponding to N and M, per fundamental line frequency cycle. A second counter is provided for generating a phase-delayed signal for adjusting the phase angle of the gate timing signals with respect to the line-frequency signal. A third counter is provided for distributing the train of pulses among the plurality of switches of the harmonic generator. The arrangement is such that the train of pulses generated by the first counter is locked to the phase-delayed signal generated by the second counter.