Variable delay device

Abstract

A variable delay device includes a variable delay circuit (12) and a correction circuit (14). On the basis of output signals R and V from variable delay lines (30, 32) of the correction circuit, an output signal V.sub.L by which a control characteristic of a variable delay line (16) is made substantially linear is outputted to the variable delay circuit from a linearity detector (34) of the correction circuit. The output signals R and V are also applied to a variable range detector (36), and on the basis of an output of the detector (36), an output signal V.sub.r by which a variable range of the variable delay line (16) is made constant is outputted to the variable delay circuit (12) from a reference level generator (38) of the correction circuit. The output signal V.sub.L determines an input/output characteristic of a non-linear circuit (22) which is included in the variable delay circuit and modifies a variable amount control signal V.sub.d, and the output signal V.sub.r is added to an output signal of the non-linear circuit by an adder (24) included in the variable delay circuit, and an adder result is applied to the variable delay line (16) as a control signal therefor.