The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 1994

Filed:

Apr. 18, 1990
Applicant:
Inventors:

Akira Kazami, Ashikaga, JP;

Osamu Nakamoto, Ohta, JP;

Hisashi Shimizu, Ohta, JP;

Katsumi Ohkawa, Ohta, JP;

Yasuhiro Koike, Gunma, JP;

Koji Nagahama, Ohta, JP;

Masao Kaneko, Maebashi, JP;

Masakazu Ueno, Ohta, JP;

Yasuo Saitou, Gunma, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
A01L / ; A01L / ;
U.S. Cl.
CPC ...
257680 ; 257678 ; 257681 ; 257723 ; 257724 ;
Abstract

A hybrid integrated circuit device is provided with: a microcomputer, a plurality of peripheral circuit elements, and a non-volatile memory which is positioned adjacent to the microcomputer, all of which are interconnected by a plurality of specified conductive paths; pair of integrated circuit substrates on which is formed the conductive paths and a casing provided with the pair of integrated circuit substrates secured to the upper and lower surfaces of the casing, forming a sealed space between these surfaces. The microcomputer and the peripheral circuit elements are positioned in the sealed space and only the non-volatile memory is positioned in an exposed space. The hybrid integrated circuit device of the present invention has a compact and simple form with a high degree of mounting density as well as superior handling capabilities and reliability.


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