High electron mobility transistor

Abstract

A semiconductor device capable of reducing element sizes exceedingly and a mask alignment accuracy in lithography is provided. This device has a pair of semiconductor layers for source/drain electrodes formed on the field insulating film so as to be respectively partially projected in a 'overhanging-shape' over the active area. For example, using an MBE method, a selectively epitaxial growth is made with these semiconductor layers as nuclei, so that first and second semiconductor layers at the interface of which a channel is formed and a pair of semiconductor layers for source and drain electrode connections can be formed. Accordingly, the semiconductor heterojunction and gate electrode can be formed in self-alignment on the active area with the semiconductor layers pair for source/drain electrodes as the reference, so that a reduction in transistor size can be realized. It is preferable that the first semiconductor layer and second semiconductor layer making a heterojunction are made of an undoped monocrystalline SiGe layer and a monosilicon layer inverse in electroconductive polarity to the substrate, respectively. The semiconductor layers for source/drain electrode connections are preferable to have a two-level structure made of a polycrystalline SiGe layer and a polysilicon layer.