The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 08, 1994
Filed:
Aug. 14, 1992
Rakesh B Sethi, Campbell, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A split floating gate EEPROM memory cell formed in a P-type silicon substrate includes source and drain buried n+ diffusion regions formed in the silicon substrate to define a substrate channel region therebetween. A layer of floating gate oxide about 400.ANG. thick is formed over the source and drain regions and over the channel region. The floating gate oxide includes a region of thin tunnel oxide about 80-100.ANG. thick formed therein over the drain region. A floating gate is formed on the floating gate oxide to extend over the channel region and includes a portion that extends over the tunnel oxide. The floating gate comprises a first layer of polysilicon about 300-600.ANG. thick, a silicon dioxide layer about 20-50.ANG. thick formed on the first layer of polysilicon, and a second layer of polysilicon about 2000.ANG. thick formed on the silicon dioxide layer. A layer of ONO is formed on the floating gate and a polysilicon control gate is formed on the layer of ONO.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile