The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 1994

Filed:

Dec. 30, 1991
Applicant:
Inventors:

Jaishankar M Menon, San Jose, CA (US);

John E Lindley, San Jose, CA (US);

Robert W Shomler, Morgan Hill, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395425 ; 395600 ; 364D / ; 3642434 ; 36424341 ; 3642419 ;
Abstract

A method for managing cache accessing of CKD formatted records that uses a Predictive Track Table to reduce host delays resulting from cache write misses. Because a significant portion of CKD formatted DASD tracks contain records having no key fields, identical logical and physical cylinder and head (CCHH) fields and similar-sized data fields, a compact description of such records by record count and length data, indexed by track, can be quickly searched to determine the physical track location of a record update that misses the cache. The Predictive Track Table search is much faster than the host wait state imposed by access and search of the DASD to read the missing track into cache. If the updated record that misses cache is found within the set of records in the Predictive Track Table, then the update may be immediately written to cache and to a Non-Volatile Store (NVS) without a DASD read access. This update then may be later destaged asynchronously to the DASD from either the cache or the NVS. Otherwise, if not found in a predictive track, the update record is written directly to the disk and the cache, subject to the LRU/MRU discipline, incurring the normal cache write-miss host wait state.


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