Single in-line dram memory module including a memory controller and

Abstract

A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W. During each refresh cycle of the DRAMs on the SIMM, enable ID logic provides a unique 2-bit ID value to the memory controller, thereby forming an ID byte. (The sum of all ID bits from each CBS.) The ID byte identifies the manufacturer of the DRAMs, their size and speed.