Virtual memory unit utilizing set associative memory structure and state

Abstract

A virtual memory unit has a plurality of directory and buffer store levels for storing page descriptor information. The memory directories and a least recently used (LRU) device constructed from the same type of standard cache address directory part include parity error detection circuits. The virtual memory unit further includes a state machine for defining sequential states used in generating control signals for directing the memory unit's operation in translating virtual addresses into physical addresses. Programmable control circuits which generate the required input data and control signals applied to the directories and LRU device for reading and updating their contents further include the retry facilities which, in response to certain types of error situations, alter state machine sequencing to again try the virtual to physical address translation with a fresh copy and the LRU replacement operations in a way to improve robustness.