The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 1994

Filed:

Apr. 14, 1993
Applicant:
Inventor:

Roland A Bechade, So. Burlington, VT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364757 ; 364758 ;
Abstract

A multiplication circuit for a floating point digital processing system includes a partial products generator and a carry adder circuit for determining a product resulting from multiplication of an M bit multiplicand and an N bit multiplier. The partial products generator outputs to the carry adder circuit partial products based on the M bit multiplicand and N bit multiplier. The carry adder circuit contains a plurality of carry adders connected in a hierarchical tree structure such that a plurality of carry adder stages are defined, with each carry adder stage except a first carry adder stage receiving adder sums from a next adjacent, lower carry adder stage in the hierarchical tree structure. The first carry adder stage receives the partial products output from the partial products generator. The multiplication circuit is optimized by employing carry select adders or carry look-ahead adders in the hierarchical tree structure.


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