The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 1994

Filed:

Dec. 26, 1990
Applicant:
Inventors:

Vilnis Klimanis, Wappingers Falls, NY (US);

Frank A Montegari, Wappingers Falls, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ; G06F / ; G11C / ;
U.S. Cl.
CPC ...
307449 ; 307463 ; 307449 ; 307465 ; 36523006 ;
Abstract

A decoder implemented using bifet technology to exhibit high performance, high density, and low power dissipation. The decoder has multiple input lines for conducting signals at ECL-compatible voltage levels and an output line for conducting signals at CMOS-compatible voltage levels. The output line is enabled in response to a predetermined combination of ECL-compatible voltage level signals on said input lines. The decoder comprises a gate for generating an OR output at ECL-compatible voltage levels according to the input line signals. An inverter is coupled to the OR gate for inverting and amplifying the OR output to produce an inverted output at CMOS voltage levels. A word line driver is coupled to an output of the inverter for isolating and driving the output line according to the inverted output. Finally, power saving means are coupled to the inverter for minimizing power dissipation in the decoder.


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