The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 01, 1994
Filed:
Feb. 14, 1992
Yi-Chi Shih, Torrance, CA (US);
David C Wang, Rancho Palos Verdes, CA (US);
Huy M Le, Monterey Park, CA (US);
Vincent Hwang, Long Beach, CA (US);
Tom Y Chi, San Gabriel, CA (US);
Hughes Aircraft Company, Los Angeles, CA (US);
Abstract
A distributed cell field-effect transistor (FET) amplifier (40) includes a plurality of parallel, elongated source (46a) and drain (46b) regions of individual FET unit cells (46) formed in a substrate (42) in transverse alternating relation, with a plurality of elongated channel regions (46c) being formed between and parallel to adjacent source (46a) and drain (46b) regions respectively. A source foot (48) and a drain foot (50) extend perpendicular to the source (46a) and drain (46b) regions on opposite longitudinally spaced sides thereof respectively. A gate foot (52) extends parallel to the source (48) and drain (50) feet, between the source foot (48) and the cells (46). Source (54) and drain (56) pads and gate (58) fingers extend from the source (48), drain (50) and gate (52) feet into electrical connection with the respective source (46a), drain (46b) and gate ( 46c) regions respectively. The source pads (54) include airbridge portions (54b) which extend over the gate foot (52) without making contact therewith. A fixed tuning circuit (70) is connected between the gate foot (52) and source foot (48), including an inductive stub (72) having a first end connected to the gate foot (52) and a second end, and a capacitor (74) having a first plate (74a) which is integral with the source foot (48) and a second plate connected to the second end of the stub (72). The integration of the capacitor (74) with the source foot (48) enables the amplifier (40) to be tuned at the gate foot (52), thereby eliminating undesirable coupling effects and the need for a separate via for the tuning circuit (70).