The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 1994

Filed:

May. 24, 1991
Applicant:
Inventors:

Koreaki Fujita, Hyogo, JP;

Shuji Murakami, Hyogo, JP;

Kenji Anami, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36523006 ; 365204 ; 307449 ;
Abstract

In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.


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