The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 1994
Filed:
Oct. 13, 1992
Bing F Ma, Sunnyvale, CA (US);
Micro Linear Corporation, San Jose, CA (US);
Abstract
An output circuit includes a totem-pole output circuit for driving a power MOSFET. A pull-up circuit and a pull-down circuit drive the output node low or high as required. The circuit prevents the pull-up and pull-down circuits from simultaneously conducting current. The pull-up circuit has a pull-up threshold voltage and the pull-down circuit has a pull-down threshold voltage such that the pull-up circuit is turned off before the pull-down circuit is activated when the output node is switched from a high state to a low state and further wherein the pull-down circuit is turned off before the pull-up circuit is activated when the output node switches from a low state to a high state. The pull-up circuit is held off when the output node is switched from a high state to a low state by two diodes from the output node to an input of the pull-up circuit. The diodes are connected in series, one diode having its anode coupled to the output node and the cathode of the other diode coupled to the input of pull-up circuit. The pull-down circuit is cut off before the pull-up Darlington drives the output from low to high by having the pull-down threshold higher than the pull-up threshold. A resistor connected between the base of the controlling transistor for the pull-up Darlington and the ground shortens the output low-to-high propagation delay time and the output rise time by shunting transient parasitic capacitance current of the pull-up controlling transistor to the ground.