Versatile peripheral bus

Abstract

An improved computer system bus is disclosed that transitions between addressed data transfers and handshake data transfers on the fly and that performs burst within dynamic data sizing during a data transfer sequence without prematurely terminating the sequence and that changes between synchronous and asynchronous data transfer sequences on the fly. These capabilities are accomplished by modifying the function of bus signal lines depending upon the type of transfer sequence undertaken. On the fly transition between addressed data transfer and handshake data transfer is accomplished by providing a set of DMA acknowledge signals and modifying their function according to the type of data transfer sequence underway. Burst within dynamic data sizing during a sequence is performed by taking advantage of burst transfer capabilities of the slave device, and the capability of the master device to modify data width on the fly. If the slave supports burst transfer, the bus master proceeds with a burst transfer sequence for the remaining portions of the data while shifting the data to accommodate the data width limitation of the slave device. On the fly transition between a synchronous transfer sequence and an asynchronous transfer sequence is accomplished by modifying the timing of bus acknowledge signals.