The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 18, 1994

Filed:

Mar. 02, 1990
Applicant:
Inventors:

Dhiru N Desai, San Jose, CA (US);

David M Lewis, Santa Cruz, CA (US);

Assignee:

Seagate Technology, Inc., Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ;
U.S. Cl.
CPC ...
395425 ; 345275 ; 365203 ; 36523003 ; 365233 ; 3652385 ; 36518902 ; 3642383 ; 3642384 ; 36492797 ; 364D / ; 371 48 ;
Abstract

A method for temporarily storing and retrieving 8-bit character information data for a magnetic disk information storage system in a number of 4.times.n DRAM buffer memory configurations. A virtual memory address for each of said 8-bit information characters is provided and each of the characters are organized into a 16-byte block. The virtual memory addresses are translated to corresponding addresses of memory locations in said 4.times.n buffer memory unit for storage of 4-bit groups of said 16-byte block in said 4.times.n DRAM buffer memory by selecting a row address for storage of said 16-byte block, by selecting a base column address for said 16-byte block, and by successively incrementing said base column address by 4 to provide additional column address for successive 4-bit groups of said 16-byte blocks. Each of said 4-bit groups of said 16-byte block are transferred through a 4-bit data bus to the various predetermined address locations in one of said 4.times.n DRAM buffer memory configurations as determined by the translating step. An 8-bit parity word for the 16-byte block is stored in a separate part of the 4.times.n memory.


Find Patent Forward Citations

Loading…