Cache memory and bus width control circuit for selectively coupling

Abstract

A bus width control circuit being arranged between a first bus and a second bus both of n-bits width, and comprising a buffer group being connected to the first bus and which split data of n-bits into partial data of m-bits and buffer them, a selector which connects each buffer to the second bus in parallel in the case where the effective data bus width of the second bus is n bits and which connects each buffer to a predetermined m bits of the second bus in the case where the effective data bus width of the second bus is m bits, and a control circuits thereof, and a control circuit which locates intact the n-bits data of the first bus in the second bus or by splitting it into partial data of m-bits in a predetermined portion of n-bits data and outputs them sequentially to the second bus, or which splits the n-bits data of the second bus into partial data of m-bits and buffers them in each buffer and then simultaneously outputs them to the first bus, or which sequentially buffers data whose m bits alone of the second bus is effective into each buffer and then simultaneously outputs them to the first bus.