The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 1994

Filed:

Jan. 06, 1993
Applicant:
Inventor:

Akira Denda, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307446 ; 307456 ; 307443 ;
Abstract

It is purposed to ensure both high speed operation and low power consumption in an output section of a Bi-CMOS type TTL logic circuit. For this purpose, impedances of a base driving part (a series circuit of a MOS transistor 9 and a resistor 11) and a collector driving part A (a resistor 12) of a bipolar transistor 1 are brought into low impedances only when the bipolar transistor 1 is changed from an off-to on-state thereof. To achieve the just-mentioned operation, potential on an output 30 is detected by an inverter 16 and on the basis of an output from the inverter 16 both MOS transistors 17, 19 are on-controlled to substantially short-circuit the resistors 11, 12. When the transistor 1 stays at its on-state, both transistors 17, 19 have been switched off, so that base and collector currents of the transistor 1 have been conducted through the resistors 11, 12 to permit the resistors 11, 12 to be greater. Thus, low power consumption is attained.


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