The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 1994
Filed:
Nov. 14, 1991
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first TFT is connected to the second memory node, and a gate of the second TFT is connected to the first data storage node, such that a flip-flip circuit is formed by the first power supply terminal, the second power supply terminal, the first TFT, the second TFT, the third TFT, and the fourth TFT, and further including data bit lines which are inverted with respect to each other, a first switching device for performing a switching operation between one of the bit lines and the first data storage node, a second switching device for performing a switching operation between the other of the data bit lines and the second data memory, and a word line device, connected to gates of the first and second switching devices, for controlling operations of the first and second switching devices.