The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 11, 1994

Filed:

Feb. 26, 1992
Applicant:
Inventors:

Udo Lieneweg, Altadena, CA (US);

Margaret A Frerking, La Canada, CA (US);

Joseph Maserjian, Valencia, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257476 ; 257 15 ; 257199 ; 257480 ; 257482 ; 257486 ; 257506 ; 257514 ; 257601 ;
Abstract

A planar frequency tripler comprised of two semiconductor diode structures connected back-to-back by an n.sup.+ doped layer (N.sup.+) of semiconductor material utilizes an n doped semiconductor material for a drift region (N) over the back contact layer in order to overcome a space charge limitation in the drift region. A barrier layer (B) is grown over the drift region, after a sheet of n-type doping (N.sub.sheet) which forms a positive charge over the drift region, N, to internally bias the diode structure. Two metal contacts are deposited over the barrier layer, B, with a gap between them. To increase the power output of the diodes of a given size, stacked diodes may be provided by alternating barrier layers and drift region layers, starting with a barrier layer and providing a positive charge sheet at the interface of a barrier on both sides of each drift region layer with n-type .delta. doping. The stacked diodes may be isolated by etching or ion implantation to the back contact layer N.sup.+ and a separate metal contact deposited on each stacked diode.


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