The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 11, 1994
Filed:
Aug. 01, 1991
Katsushi Asahina, Hyogo, JP;
Masahiro Ueda, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
Disclosed is an improved Bi-CMOS gate array for increasing integration density. The gate array includes a predetermined region for forming PMOS transistors, a predetermined region for forming bipolar transistors, a predetermined region for forming resistance elements, and a predetermined region for forming NMOS transistors. The resistance element region is formed adjacent to the bipolar transistor region, and, therefore, it is not necessary to provide any interconnection for forming a logic circuit including the resistance element connected to the bipolar transistor. An area occupied by interconnections on the semiconductor substrate is thus reduced, and, therefore the integration density is increased.