Fast access memory structure

Abstract

A memory chip, comprising a chip memory section organized to hold a plurality of separate blocks of data, with each of the data blocks containing M individual data units; a circuit for addressing a given block of data in the chip memory section; and an N data unit chip parallel output interface from the memory chip where N is less than M, and N is greater than one. The memory chip further comprises a chip register for receiving from the chip memory section at least a portion of an addressed block of data, which portion comprises P data units, where P is greater than N, the chip register having P register stages for holding the P data units of the addressed data block, wherein the P register stages are grouped into at least a first and second groups of stages, with no group of stages comprising more than N register stages and with at least one of the groups of register stages having a plurality of stages. The memory chip also includes a gating structure for gating the respective groups of stages to the N data unit parallel output interface, the gating structure including at least a first gate circuit for gating in parallel the data units held in the first group of stages to the N data unit parallel output interface in accordance with a TOGGLE logic signal, and a second gate circuit for gating in parallel the data units held in the second group of stages to the N data unit parallel output interface in accordance with a NOT TOGGLE logic signal.