The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 1994

Filed:

Apr. 20, 1990
Applicant:
Inventors:

Koichi Okazawa, Tokyo, JP;

Hiroaki Aotsu, Yokohama, JP;

Hitoshi Kawaguchi, Yokohama, JP;

Masami Jikihara, Ebina, JP;

Kazushi Kobayashi, Ebina, JP;

Koichi Kimura, Yokohama, JP;

Tetsuya Mochida, Yokohama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395325 ; 364D / ; 364228 ; 364229 ; 364230 ; 3642301 ; 3642302 ; 3642304 ; 3642315 ; 364240 ; 3642405 ; 3642412 ; 3642413 ; 3642426 ; 3642427 ; 3642429 ; 36424292 ; 364260 ; 3642601 ; 3642705 ; 3642706 ; 3642716 ; 3642717 ;
Abstract

A bus system for an information processing system in which data transfer among plurality of modules is controlled on a common bus. In response to a bus use request from a module, a command is issued for aborting data transfer being performed by another module having a lower priority. The module which is transferring the data responds to the abort command by issuing a signal indicating that a word being transferred is the final word. The data is transferred between a master and a slave through an address bus having a same width as the data in synchronism with a clock supplied from a bus controller.


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