The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 1994
Filed:
Jan. 31, 1991
C David Wang, Melville, NY (US);
James Thompson, Greenlawn, NY (US);
AIL Systems, Inc., Deer Park, NY (US);
Abstract
An adaptive probabilistic neural network (APNN) includes a cluster processor circuit which generates a signal which represents a probability density function estimation value which is used to sort input pulse parameter data signals based upon a probability of obtaining a correct match with a group of input pulse parameter data signals that have already been sorted. In the APNN system, a pulse buffer memory circuit is contained within the cluster processor circuit and temporarily stores the assigned input pulse parameter data signals. The pulse buffer memory circuit is initially empty. As the input pulse parameter data signals are presented to the APNN, the system sorts the incoming data signals based on the probability density function estimation value signal generated by each currently operating cluster processor circuit. The current input pulse parameter data signal is sorted and stored in the pulse buffer memory circuit of the cluster processor circuit. A small probability density function estimation value signal indicates the current unassigned input pulse parameter data signal is not recognized by the APNN system. A large probability density function estimation value signal indicates a match and the current input pulse parameter data signal will be included within a particular cluster processor circuit.