The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 04, 1994

Filed:

Aug. 14, 1992
Applicant:
Inventors:

Hisashi Ogawa, Katano, JP;

Yasushi Naito, Toyonaka, JP;

Masanori Fukumoto, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437195 ; 437 40 ; 437 52 ; 437228 ; 437978 ; 437984 ; 437982 ; 156644 ; 156653 ;
Abstract

A fabrication method for a semiconductor integrated circuits which permits the self-aligned formation of contact windows without causing shorts or breaks in the interconnecting lines in the device is provided. After forming gate electrodes and source/drain regions of transistors on a semiconductor substrate, an etch-stop layer and a BPSG film are successively deposited over the gate electrodes and the source/drain regions. After a resist having a contact window pattern is formed on the BPSG film, an isotropic dry etching using a microwave plasma is performed to etch the BPSG film. According to the isotropic dry etching, the laterally etching rate in the BPSG film can be controlled by adjusting the RF power, and a silicon dioxide film can be used as the etch stop layer. After the BPSG flow process, the etch stop layer on the contact region is etched away to form contact windows.


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