The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 04, 1994
Filed:
Jul. 12, 1991
Carl Cederbaum, Paris, FR;
Roland Chanclou, Perthes, FR;
Myriam Combes, Evry, FR;
Patrick Mone, Ponthierry, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure including: a semiconductor substrate (18/19) having active regions (21) of devices (T1, . . . ) therein and/or polysilicon lines (23-1, . . .) formed thereupon; a first thick passivating layer (26/27) formed above the substrate having a set of first metal contact studs (30-1, . . .) therein contacting at least one of the active regions (21) and/or the polysilicon lines (23-1, . . . ); the surface of the first contact studs is coplanar with the surface of the first passivating layer; a plurality of polysilicon lands (31-1, . . .) formed on the planar structure in contact with the first contact studs; the polysilicon lands are either highly resistive, highly conductive or a mix thereof; a second thick passivating layer (34/35) formed above the resulting structure having a set of second metal contact-studs (37-1 . . .) therein contacting at least one of the polysilicon lands and/or one of the first contact studs; the surface of the second contact studs is coplanar with the surface of the second thick passivating layer. a plurality of metal lands (38-1, . . . ) formed above the second thick passivating layer (34/35) in contact with the second contact studs; a final insulating film (39). The structure of the present invention may be advantageously used in chips implementing four device SRAM cells with stacked polysilicon load resistors (4D/2R SRAM cells) in CMOS FET technology. The present invention also relates to the method for fabricating the same.