The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 28, 1993

Filed:

Feb. 18, 1993
Applicant:
Inventors:

Naoki Kashimura, Tokyo, JP;

Takamitsu Sakai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395142 ; 395141 ; 345144 ;
Abstract

An outline compensation circuit comprising: a first coefficient multiplier for reducing a level of an image signal by one half and reversing the polarity thereof; a first delay circuit for delaying by 2.tau. the signal from the first coefficient multiplier; a first adder for adding the signal from the first delay circuit to the image signal; a second delay circuit for delaying the signal from the first adder by 2.tau.; a second adder for adding the signal delayed by the second delay circuit to the signal from the first coefficient multiplier to output a second-order differential signal of the image signal; a first non-linear converter for calculating the square root of the second-order differential signal from the second adder; a subtractor for subtracting the signal from the first delay circuit from the signal from the first coefficient multiplier to output a first-order differential signal of the image signal; an absolute value calculating circuit for calculating the absolute value of the first-order differential signal from the subtractor; a third delay circuit for delaying the signal from the absolute value calculating circuit by .tau.; a second non-linear converter for calculating the square root of the signal from the third delay circuit; and a multiplier for multiplying the signal from the second non-linear converter with the signal from the non-linear converter to output an outline compensation signal, whereby outline compensation can be carried out naturally.


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