Pipelined a/d converter

Abstract

There is disclosed a pipelined A/D converter including a plurality of A/D-D/A sub-blocks and one A/D sub-block successively connected in cascade form to determine a conversion output by several partial bits beginning from the most significant bit. Each of A/D-D/A sub-blocks includes a sample-and-hold circuit for successively sampling and holding an input analog signal fed to the sub-block, a partial A/D converter for performing A/D conversion on a hold output of this sample-and-hold circuit, a latch circuit for latching outputs of the partial A/D converter, a D/A converter for inversely converting outputs of the latch circuit to an analog signal, and a chopper amplifier for sampling the hold output of the sample-and-hold circuit with a delay of half a period, amplifying a difference between the sampled value and the inverse conversion output of the D/A converter during a succeeding interval of amplify mode, and outputting the amplified difference to a sub-block of a succeeding stage as a conversion residue.