The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 28, 1993
Filed:
Jul. 17, 1992
Kenji Sekine, Nishitama, JP;
Masami Ohnishi, Hachiouji, JP;
Haruhiko Funaki, Tanashi, JP;
Nobuo Masuda, Higashimurayama, JP;
Akio Iso, Yokosuka, JP;
Hitachi, Ltd., Tokyo, JP;
Space Communications Research Corporation, Tokyo, JP;
Abstract
A high-frequency power amplifier comprises a pair of FETs, a divider which supplies opposite-phase versions of a signal to be amplified to the FETs, distributed-parameter transmission lines connected respectively at one ends thereof to output electrodes of the FETs, and a combiner which combines signals appearing at another ends of the transmission lines into a signal of a common phase. Stubs which short-circuit for even harmonics included in output signals of the FETs are connected respectively to the transmission lines at positions distant from the output electrodes of the FETs by a multiple of a quarter wavelength of the fundamental wave included in the output signals of the FETs. A first capacitor is connected between the transmission lines at positions distant from the output electrodes of the FETs by the 1/12 wavelength of the fundamental wave included in the output signals of the FETs so that the output electrodes of the FETs are open for the third harmonic, and a second capacitor is connected between the transmission lines at positions between the connecting positions of the first capacitor and the connecting positions of the stubs so as to perform impedance matching for the fundamental wave included in the output signals of the FETs.