The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1993
Filed:
Dec. 24, 1990
Steve Bush, San Jose, CA (US);
Robert Shur, Los Altos, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
An event-driven logic simulator provides for future evaluation events. Evaluation latencies are assigned to respective inputs of components based on component type. At least some of these latencies are positive and finite. When a signal status event specifies a change at an input associated with a positive latency, the function for the component is not evaluated at the present time. Instead, the evaluation is postponed to a future time equal to the present time plus the assigned latency. The evaluation is thus latent until the scheduled time becomes present. When multiple evaluation events are indicated for a common component output, a queue manager resolves the conflicts by discarding all but one of the evaluation events for that output. This approach minimizes redundant and superfluous evaluations during circuit simulation.