The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 1993
Filed:
Oct. 31, 1990
Shinji Emori, Urawa, JP;
Masaya Tamamura, Inagi, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A controllable delay logic circuit includes a differential circuit having first and second transistors, a first load coupled between a first power supply line and the collector of the first transistor, a second load coupled between the first power supply line and the collector of the second transistor, and a constant-current source connected between a second power supply line and the emitters of the first and second transistors. The controllable delay logic circuit also includes a first power source, a first current path circuit having a first resistor and selectively allowing a first current to pass through the first transistor from the first power source via the first resistor, and a second current path circuit having a second resistor and selectively allowing a second current to pass through the second transistor from the first power source via the second resistor.