Dram peripheral circuit contact aspect ratio improvement process

Abstract

A method and resulting structure for defining a dielectric layer thickness and etching openings having a desired aspect ratio through said dielectric layer covering regions in the peripheral circuits of a DRAM integrated circuit to be electrically contacted in a semiconductor wafer is described. The DRAM integrated circuit including the peripheral circuits to be electrically contacted is provide in the semiconductor wafer. A first conductive polysilicon layer is formed over said DRAM integrated circuit and the layer is patterned to leave the layer over the peripheral circuits. A first interlevel dielectric layer is formed over the polysilicon layer which has been patterned. A second conductive polysilicon layer is formed over the first interlevel dielectric layer and patterned to leave the layer over areas other than the peripheral circuits. The first interlevel dielectric layer and first polysilicon layer thereunder are masked and etched to remove the first interlevel dielectric layer and first polysilicon layer from all the peripheral circuits. A second interlevel dielectric layer is formed over the exposed second conductive polysilicon layer, first interlevel dielectric and semiconductor wafer. The openings having a desired aspect ratio are etched through said second interlevel dielectric layer.