The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 07, 1993

Filed:

Nov. 12, 1992
Applicant:
Inventors:

Dayo Alugbin, Bethlehem, PA (US);

Franklin D Nkansah, Allentown, PA (US);

Kolawole R Olasupo, Kutztown, PA (US);

Assignee:

AT&T Bell Laboratories, Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437228 ; 437194 ; 437235 ; 437947 ; 437981 ; 156644 ;
Abstract

A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.


Find Patent Forward Citations

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Alugbin, Dayo. (1993). Method of integrated circuit fabrication having planarized dielectrics (U.S. Patent No. 5268332). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5268332

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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