The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 07, 1993
Filed:
Nov. 08, 1991
Applicant:
Inventors:
Sailesh Chittipeddi, Whitehall, PA (US);
Michael J Kelly, Orefield, PA (US);
Assignee:
AT&T Bell Laboratories, Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437195 ; 437190 ; 437197 ; 437200 ;
Abstract
A conductive layer is formed beneath a runner in an integrated circuit. The conductive layer is also formed within vias. The conductive layer preserves electrical connection should the runner separate due, perhaps, to electromigration or stress voiding. The conductive layer also provides protection against various failures or defects which may occur in the runner material within the vias.
Chittipeddi, Sailesh. (1993). Method of fabricating an integrated circuit interconnection (U.S. Patent No. 5268329). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5268329
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile