Sense amplifier control circuit of a semiconductor memory device

Abstract

A sense amplifier control circuit for controlling the voltage applied to a sense amplifier and a memory cell by setting the voltage as a given level (in this case, 4 V) is provided. The sense amplifier control circuit being inputted by the voltage applied to the sense amplifier and the memory cell thereto and generating the output voltage to the gate of the sense amplifier driver includes a comparator for operating whenever the voltage applied to the sense amplifier and memory cell is varied, a level shift circuit for converting an internal power voltage into an external power voltage, a trigger circuit, a driver control circuit and a bias circuit for constantly maintaining the current flowing into the driving element of the driver control circuit. Therefore, the voltage applied to the sense amplifier and memory cell come to have an appropriate rising slope, and after reached to the given level, the control circuit controls the level to be continuously maintained. Consequently, the wrong operation of a chip and the power noise is reduced, to thus improve the reliability of a semiconductor memory device.