Rational fraction synthesizer

Abstract

A frequency synthesizer with at least one main Phase Locked Loop (PLL), where the PLL has programmable dividers in both its input path (M) and its feedback path (N), and where the main PLL is driven by a reference source of frequency F.sub.ref and has output F.sub.out =.sup.N /.sub.M *F.sub.ref, and each of the programmable counters is controlled by a calculation and control device. The synthesizer uses a method to produce an output frequency F.sub.out that is a close approximation to a requested frequency F.sub.req, including calculating several integer approximations .sup.N i/M.sub.i to the ratio .sup.F req/F.sub.ref, and picking the best approximation where the values of N.sub.i and M.sub.i are both still small enough to be used to program the two programmable counters. In another form of the invention, there is an adjustable reference source which can provide a plurality of reference frequencies F.sub.refj under control of the calculation and control device. Here, a value of F.sub.refj is chosen, and then the approximation and picking steps are run, followed by a calculation of the resulting error (err=F.sub.out -F.sub.req). Then, by selecting a new F.sub.refj, the procedure can be run again, resulting in a new err value. After several runs, each with its assigned error, one of the low error runs can be chosen, and the corresponding M.sub.i and N.sub.i values used the program the counters.