The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 1993
Filed:
Apr. 17, 1991
Applicant:
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364491 ; 364490 ; 364489 ; 364488 ;
Abstract
A method for layout compaction which comprises steps of establishing storage areas in a direct access memory as a boundary information memory to which geometrical information on boundaries of a layout is written, searching layout elements of groups adjoining the boundaries of the layout and performing a processing of packing layout elements in a bottom boundary region of the layout and of packing layout elements in a top boundary region of the layout by using the boundary information memory. Thereby, a compaction of the layout can be performed at a high speed.
Sato, Koichi. (1993). Method for vlsi layout pattern compaction by using direct access memory (U.S. Patent No. 5267177). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5267177
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile