The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1993

Filed:

Jun. 30, 1992
Applicant:
Inventors:

Hoan A Au, Palo Alto, CA (US);

Arvind M Patel, San Jose, CA (US);

Robert A Rutledge, San Jose, CA (US);

Bum S So, San Jose, CA (US);

Albert S Su, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
307511 ; 307269 ; 307262 ; 307261 ; 307603 ; 328 63 ;
Abstract

Method and circuitry for phase synchronizing an analog input signal with a clock signal by sensing clock delay error, adjusting in increments clock delay trim of a delay element that initially has an arbitrary delay setting, and stopping adjustment after differential delay between the signals has been eliminated.


Find Patent Forward Citations

Au, Hoan. (1993). Clock delay trim adjustment with stopping feature for eliminating (U.S. Patent No. 5266850). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5266850

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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