The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1993

Filed:

Nov. 08, 1991
Applicant:
Inventors:

Brian G Bagley, Watchung, NJ (US);

Robert B Marcus, Murray Hill, NJ (US);

Tirunelveli S Ravi, Eatontown, NJ (US);

Assignee:

Bell Communications Research, Inc., Livingston, NJ (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437228 ; 437 73 ; 156651 ;
Abstract

A method of fabricating a self-aligned gated electron field emitter. An oxidation process forms an optimized, atomically sharp needle (18) in a silicon substrate (12). The needle and surrounding planar area are conformally coated with silicon dioxide (22). A dielectric layer (24) is deposited and planarized over the needle. The dielectric layer is then partially etched away so as to expose the coated needle. The silicon dioxide exposed on the needle is isotropically etched so as to undercut the dielectric layer. A gate metal is directionally deposited so as to form a gate layer (26) on the planar portions of the dielectric layer that is electrically isolated from the gate metal (28) deposited on the needle. The metal on the needle is anodically etched by applying the potential only to the silicon and not to the gate layer. Electro-plating may recoat the needle with another metal (30). The silicon substrate may be replaced by a glass substrate (42) on which is deposited a polysilicon or amorphous silicon layer (40). The invention allows the fabrication of an array of emitters with closely spaced gates over large areas and on inexpensive substrates.


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