The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 30, 1993

Filed:

Jun. 25, 1992
Applicant:
Inventor:

Andre I Nasr, Marlboro, MA (US);

Assignee:

Digital Equipment Corporation, Maynard, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
156656 ; 437200 ; 437918 ; 148D / ;
Abstract

Methods of forming local interconnects and high resistor polysilicon loads are disclosed. The local interconnects are formed by depositing a layer of polysilicon over CoSi.sub.2 in partially fabricated semiconductor wafers. The polysilicon is then coated with cobalt and annealed to form a second layer of of CoSi.sub.2. The method can be expanded to form a high resistor polysilicon load by depositing and patterning an oxide layer to form contact windows before application of the polysilicon layer. Another oxide layer is deposited over the polysilicon and patterned before application of the cobalt layer to define the areas which create the resistor load.


Find Patent Forward Citations

Nasr, Andre. (1993). Methods of forming a local interconnect and a high resistor polysilicon (U.S. Patent No. 5266156). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5266156

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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