The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 23, 1993

Filed:

Feb. 27, 1992
Applicant:
Inventors:

Gon Son, Kyungki, KR;

Heon C Lee, Kyungki, KR;

Soo S Yoon, Seoul, KR;

Dong D Lee, Seoul, KR;

Hae S Park, Seoul, KR;

Sea C Kim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437195 ; 437228 ; 437235 ; 437978 ;
Abstract

A method of forming a contact region having an insulating layer which is etch protected, which includes sequentially depositing a gate oxide layer 2, a first conducting layer 3 for gate electrode, a first insulating layer 4 and a second conducting layer 5 on a silicon substrate 1. A portion of the second conducting layer 5 is etched to form an etch protective layer 5A. Portions of the etch protective layer 5A, the first insulating layer 4 and the first conducting layer 3 are sequentially etched to form separated gate electrodes 3a and 3b and separated etch protective layers 5a and 5b on the gate electrodes 3a and 3b, respectively and to expose a portion of the gate oxide layer 2 to define a source region 1A. A second insulating layer 6 is deposited on the entire surface of the resulting structure. The second insulating layer 6 is etched to form a spacer 6a on each of the side walls of the gate electrodes 3a and 3b and on the first insulating layer 4 and to expose the source region 1A. A third insulating layer 7 is deposited on the entire surface of the resulting structure. A contact region 10 is formed by selectively removing the third insulating layer 7 and the gate oxide layer 2 on the source region 1A and portions of the third insulating layer 7 on the etch protective layers 5a and 5b to form a contact region having an etch protected insulating layer.


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