The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1993

Filed:

Apr. 21, 1992
Applicant:
Inventors:

Walter L Gregory, Jr, Loveland, CO (US);

Jay M Stepleton, Boulder, CO (US);

Davis M Glasgow, Loveland, CO (US);

Kay C Lannen, Fort Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
3241 / ; 324 731 ; 3241 / ;
Abstract

A system and method for calibrating testers. A reference timing signal and an internal timing signal used in tester calibration are generated within a tester. A first calibration is performed wherein test module channel characteristics are measured and recorded, and an adjustment value is determined to correct the time placement of the internal timing signal. Driver and receiver delays are adjusted based on the characteristics measured in this first calibration, and the internal timing signal is adjusted as well. A second calibration is performed wherein temporal relationships between the adjusted internal timing signal and signals at the test module channel mint pins are determined. Driver and receiver delays are adjusted based on the results of this calibration. An optional calibration is performed wherein temporal relationship between the adjusted internal timing signal and signals at the board-interface end of a test fixture are measured. Using these measurements and the measurements obtained in the second calibration, a test fixture characterization is performed and recorded. Delays of the drivers and receivers are again adjusted to account for the fixture characteristics. Additional calibration methods provided by the present invention include a manual multi-module calibration to keep test module channels aligned when a new module is designated as the master module, and a manual synchronization clock calibration to deskew drivers and receivers relative to an external clock supplied by the device under test.


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