The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 16, 1993

Filed:

Apr. 17, 1992
Applicant:
Inventors:

Masaru Wakatabe, Saitama, JP;

Mitsugu Tanaka, Saitama, JP;

Shinji Kunori, Saitama, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257483 ; 257622 ; 257916 ; 257484 ; 257623 ;
Abstract

A semiconductor rectifier having a high breakdown voltage and a high speed operation is provided, which includes a semiconductor substrate having an N.sup.+ -type semiconductor layer and an N-type semiconductor layer, a P.sup.+ -type semiconductor layer formed in the N-type semiconductor layer to provide a PN junction therebetween, the P.sup.+ -type semiconductor layer defining exposed regions of the N-type semiconductor layer, and a metal layer provided on an entire surface of the semiconductor substrate having the P.sup.+ -type semiconductor layer to provide contact surfaces of Schottky barrier between the metal layer and each of the exposed regions of the N-type semiconductor layer. In the structure, a configuration of the PN junction is provided to satisfy conditions given by 0.degree.<.theta..ltoreq.135.degree. and 3Wbi.ltoreq.W.ltoreq.2W.sub.B where .theta. is an angle between one of the contact surfaces and a tangent line passing through a point f on the PN junction through which a straight line passes from a top of a built-in depletion layer in parallel with each of the contact surfaces and where W.sub.bi is a thickness of the built-in depletion layer extending to the N-type semiconductor layer at zero bias voltage, W is a width of each of the contact surfaces and W.sub.B is a thickness of a depletion layer at breakdown of the pn junction, respectively.


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