Multiprocessor communications register providing complete access in a

Abstract

In a multiprocessor system, a communication register is partitioned into groups of word storage locations and one of the groups is further partitioned into subgroups associated respectively with the processors. An access controller accesses any groups of the communication register when a system program is being processed and accesses one of the subgroup when a user program is being processed. A write controller is responsive to a test & set instruction of first occurrence from a common bus for assembling a lock work with a data word, a control field and a counter field containing a variable count. The control field of the lock word is set to a first binary state when it is assembled and reset to a second binary state when deassembled. In response to a load instruction from the common bus, either the data word from the bus or lock word is stored into a specified storage area of a communication register. A read controller reads contents of an addressed location of the communication register onto the common bus in response to a save instruction. Test & set instruction of a subsequent occurrence causes the variable count in the stored lock word to be decremented as long as the control field remains set to the first binary state. When the count reduces to zero, a signal is applied to the common bus indicating the occurrence of a dead lock.